Hardware architectures range from superconducting loops to topological qubits
Hardware architectures for quantum chips rely on distinct physical modalities, primarily superconducting circuits, silicon spin traps, neutral atoms, and experimental topological systems.
Superconducting designs currently dominate commercial installations. Engineers fabricate these chips by printing microscopic loops separated by thin insulating barriers known as Josephson junctions. These junctions function as non-linear inductors, isolating individual quantum energy levels that act as artificial atoms controlled by microwave pulses.
According to IBM’s May 15, 2025 deployment report with the University of Tokyo, the 156-qubit IBM Heron processor features a tunable-coupler architecture that delivers a 3- to 4-fold reduction in two-qubit error rates compared to the previous Eagle processor. Tunable couplers allow system operators to dynamically activate or suppress interactions between neighboring qubits, reducing background noise and computational crosstalk during multi-gate routines.
According to Google Quantum AI’s December 9, 2024 specification sheet, its 105-qubit superconducting quantum chip named Willow achieves an average single-qubit gate error rate of 0.035%. Achieving low physical error rates remains necessary to assemble reliable logical qubits across any fabrication format.
Other engineering teams pursue silicon spin architectures that capture isolated electrons inside modified semiconductor quantum dots. This strategy attempts to leverage mature commercial microchip fabrication facilities to manufacture billions of uniform quantum elements. Meanwhile, researchers are attempting to build topological quantum chips that braid theoretical quasiparticles to shield data from local environmental disturbances.
- Superconducting circuits: Planar microchips etched with Josephson junctions that manipulate electromagnetic energy states via microwave frequencies.
- Silicon spin chips: Nanoscale semiconductor devices that trap single electrons and encode information using magnetic spin orientations.
- Trapped ion devices: Vacuum chambers using optical laser grids to suspend and manipulate isolated atomic ions.
- Topological systems: Experimental semiconductor-superconductor interfaces designed to encode data in protected non-local spatial properties.
Why do quantum computing chips need extreme cooling?
Quantum computing chips require near-absolute-zero operating environments because ambient thermal energy destroys the fragile quantum states that allow qubits to calculate.
Heat causes atomic vibrations within the chip substrate and generates stray electromagnetic radiation. When a qubit absorbs thermal energy from its surroundings, its phase collapses in a breakdown called decoherence. Once decoherence occurs, the chip loses its mathematical data and functions no better than a broken classical register.
According to the National Institute of Standards and Technology (NIST), superconducting quantum processors require commercial dilution refrigerators operating at base temperatures below 20 to 100 millikelvin to suppress thermal excitations and prevent qubits from losing coherence. These multi-stage cryostats achieve temperatures colder than the vacuum of deep space by circulating a closed mixture of helium isotopes.
Physical wiring and thermal loads between room-temperature electronics and dilution refrigerators represent a critical scaling bottleneck for multi-qubit processors. Every individual control line carries ambient heat downward, threatening to warm the mixing chamber.
Engineers are developing cryogenic integrated circuits to manage signal routing inside the refrigerator itself. According to Intel’s June 2024 report at the IEEE Symposium on VLSI Technology & Circuits, the Pando Tree cryogenic control chip was engineered to operate directly at 10 to 20 millikelvin, demultiplexing control signals across up to 64 qubit terminals to reduce wiring congestion.
Moving the multiplexing circuitry directly adjacent to the quantum chip eliminates hundreds of analog cables.
Quantum processors complement classical CPUs rather than replacing them
Quantum processors function as specialized mathematical accelerators that work alongside traditional microprocessors rather than replacing everyday consumer CPUs.
A quantum chip cannot run an operating system, drive an external display, or handle basic database lookups. According to NIST, superconducting quantum processors require commercial dilution refrigerators operating at base temperatures below 20 to 100 millikelvin. In real deployments, classical servers control the initialization, calibration, pulse timing, and final readout collection of the QPU.
Hybrid workflows route subroutines based on algorithmic suitability. Analyzing how quantum and classical computing differ explains why classical chips retain everyday application workloads while offloading targeted linear algebra and quantum simulations. This architecture mirrors the division of labor between standard central processors and dedicated graphics processing units.
Physical infrastructure constraints restrict quantum chips to centralized enterprise data centers. Dilution refrigerators require three-phase industrial electrical power, extensive vacuum pump assemblies, and continuous access to specialized gas supplies. Enterprise developers access QPUs through cloud environments, submitting complex optimization or chemical modeling tasks while standard computer servers handle the surrounding software stack.
Sabine Hossenfelder breaks down Microsoft’s Majorana 2 chip claims
Physicist Sabine Hossenfelder analyzed Microsoft’s Majorana 2 announcement, assessing the validity of the company’s claims regarding topological qubits and operational readiness.
Microsoft positioned Majorana 2 as a topological quantum chip engineered with help from its agentic AI tools. According to Sabine Hossenfelder, Microsoft stated that the device sustained an average qubit lifespan of 20 seconds alongside a 1,000-fold gain in stability. Microsoft also announced its goal to construct a scalable quantum machine by 2029, accelerating its prior target of 2033.
Hossenfelder observed that while Google, Amazon, and IBM build chips using superconducting circuits, Microsoft has focused on topological computing for more than a decade. Topological computing relies on conserved quantities like topological invariants or boundary conditions to protect hardware from environmental decoherence.
However, Hossenfelder identified large discrepancies between Microsoft’s marketing statements and its underlying experimental evidence. Microsoft’s previous Majorana 1 announcement faced widespread criticism because the accompanying technical paper lacked verification data for even a single working qubit. According to Sabine Hossenfelder, Microsoft later claimed to create a qubit with four Majorana modes in an unverified preprint that drew sharp scientific skepticism.
Microsoft’s recent technical paper details a hardware material shift from aluminum to lead, which extends quantum effects by widening the superconducting gap. Yet Hossenfelder emphasized that observing topological states does not equal operating an actual topological qubit, as Microsoft has not demonstrated both properties simultaneously.
Condensed matter physicist Henry Legg informed Science News that the preprint fails to resolve the primary scientific challenges. Physicist Sergey Frolov told Scientific American that “this new preprint is not based on a research track record that can be considered a solid foundation.”
Frolov added that “when Microsoft is mentioned these days, physicists and quantum computing specialists just chuckle or raise their eyebrows.”
Sabine Hossenfelder rated the research paper a two out of 10 on her scale of exaggeration, while scoring Microsoft’s press release an eight out of 10. According to Sabine Hossenfelder, Microsoft’s claims resemble a progress bar stuck at 99% that could remain unresolved for the next 20 years.
